Soft Error Impact on FinFET and CMOS XOR Logic Gates
نویسندگان
چکیده
منابع مشابه
Design Analysis of XOR Gates Using CMOS & Pass Transistor Logic
This paper compares two different logic styles based on 45 nm technology for implementing logic gates of upto two inputs in terms of their layout area, delay and power dissipation. The XOR gate has been implemented & designed using CMOS & Pass Transistor logic on 45 nm technology .The schematic of proposed gate has been designed & simulated by using DSCH3& its equivalent layout has been develop...
متن کاملSOFT-ERROR SUSCEPTIBILITY OF FinFET SRAMs
INTRODUCTION For technology scaling beyond 20 nm, FinFET transistors will replace the conventional planar geometry. The driving force for the introduction of FinFET architecture is the superior immunity to short-channel effects and the reduction of the effects of process variation on device performance exhibited by the FinFET.[1-4] Figure 1 shows a comparison of architectures of the planar FET ...
متن کاملImplementation Of Xor Gate Using Cmos Logic
Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is The dual rail toffoli gate is designed using transmission gate. minimum sized XOR gate is implemented at 0.12ìm. solving the problems. Transmission Gate (TG) uses to realize complex logic functions by using a small number It is implemented in Standard CMOS logic (3). Proposed CLA imple...
متن کاملAnalysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology
As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...
متن کاملDesign of Near-Threshold CMOS Logic Gates
Numerous efforts have made to balance the tradeoff between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the desig...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of Integrated Circuits and Systems
سال: 2020
ISSN: 1872-0234,1807-1953
DOI: 10.29292/jics.v15i2.131